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<a href="sys_8h.html">Go to the documentation of this file.</a><div class="fragment"><div class="line"><a name="l00001"></a><span class="lineno">    1</span>&#160;<span class="preprocessor">#ifndef _SYS_H</span></div><div class="line"><a name="l00002"></a><span class="lineno">    2</span>&#160;<span class="preprocessor">#define _SYS_H</span></div><div class="line"><a name="l00003"></a><span class="lineno">    3</span>&#160;</div><div class="line"><a name="l00004"></a><span class="lineno">    4</span>&#160;<span class="preprocessor">#include &lt;stdint.h&gt;</span></div><div class="line"><a name="l00005"></a><span class="lineno">    5</span>&#160;</div><div class="line"><a name="l00006"></a><span class="lineno">    6</span>&#160;</div><div class="line"><a name="l00007"></a><span class="lineno">    7</span>&#160;</div><div class="line"><a name="l00008"></a><span class="lineno">    8</span>&#160;</div><div class="line"><a name="l00009"></a><span class="lineno"><a class="line" href="sys_8h.html#ab6b652797b16c31087c6e7fef45cc175">    9</a></span>&#160;<span class="preprocessor">#define CPU_FREQ 450000000 // Hz</span></div><div class="line"><a name="l00010"></a><span class="lineno">   10</span>&#160;</div><div class="line"><a name="l00011"></a><span class="lineno">   11</span>&#160;</div><div class="line"><a name="l00012"></a><span class="lineno">   12</span>&#160;</div><div class="line"><a name="l00013"></a><span class="lineno">   13</span>&#160;</div><div class="line"><a name="l00014"></a><span class="lineno">   14</span>&#160;<span class="comment">/* ccm */</span></div><div class="line"><a name="l00015"></a><span class="lineno"><a class="line" href="sys_8h.html#a035e6508d3f8c8b73178b4d298c9b049">   15</a></span>&#160;<span class="preprocessor">#define CCM_BASE    0x01c20000</span></div><div class="line"><a name="l00016"></a><span class="lineno"><a class="line" href="sys_8h.html#a32474293ccb055759dc4ca2ca74329a4">   16</a></span>&#160;<span class="preprocessor">#define R_PRCM_BASE     0x01f01400</span></div><div class="line"><a name="l00017"></a><span class="lineno">   17</span>&#160;</div><div class="line"><a name="l00018"></a><span class="lineno">   18</span>&#160;<span class="comment">/* clock gating */</span></div><div class="line"><a name="l00019"></a><span class="lineno"><a class="line" href="sys_8h.html#a2656cc632331a4d493cd9cdf000b7ab9">   19</a></span>&#160;<span class="preprocessor">#define BUS_CLK_GATING_REG0         (CCM_BASE + 0x060)</span></div><div class="line"><a name="l00020"></a><span class="lineno"><a class="line" href="sys_8h.html#a871efa0140020390f52dac43d5a49a83">   20</a></span>&#160;<span class="preprocessor">#define BUS_CLK_GATING_REG1         (CCM_BASE + 0x064)</span></div><div class="line"><a name="l00021"></a><span class="lineno"><a class="line" href="sys_8h.html#af78c33d217832cde5f408a6343d98483">   21</a></span>&#160;<span class="preprocessor">#define MSGBOX_GATING           BIT(21)</span></div><div class="line"><a name="l00022"></a><span class="lineno"><a class="line" href="sys_8h.html#adb54dfeab3c7f9b509a952a123fc5524">   22</a></span>&#160;<span class="preprocessor">#define BUS_CLK_GATING_REG2         (CCM_BASE + 0x068)</span></div><div class="line"><a name="l00023"></a><span class="lineno"><a class="line" href="sys_8h.html#a999392ad3a7f35dbae0eef27a24fef4e">   23</a></span>&#160;<span class="preprocessor">#define PIO_GATING          BIT(5)</span></div><div class="line"><a name="l00024"></a><span class="lineno"><a class="line" href="sys_8h.html#a7f4f7a1fef4b8fab540c50af006d7722">   24</a></span>&#160;<span class="preprocessor">#define THS_GATING          BIT(8)</span></div><div class="line"><a name="l00025"></a><span class="lineno"><a class="line" href="sys_8h.html#a51221cc3051e99316cdeee92511b51cc">   25</a></span>&#160;<span class="preprocessor">#define BUS_CLK_GATING_REG3         (CCM_BASE + 0x06c)</span></div><div class="line"><a name="l00026"></a><span class="lineno"><a class="line" href="sys_8h.html#a3514019cb4697107d7eced60cc5abcf4">   26</a></span>&#160;<span class="preprocessor">#define UART0_GATING            BIT(16)</span></div><div class="line"><a name="l00027"></a><span class="lineno"><a class="line" href="sys_8h.html#a414fab8d1a2fd774ca9fe74bf3856c46">   27</a></span>&#160;<span class="preprocessor">#define I2C0_GATING             BIT(0)</span></div><div class="line"><a name="l00028"></a><span class="lineno"><a class="line" href="sys_8h.html#a21db4eddb5409b4ecc6ec8439afe6ed1">   28</a></span>&#160;<span class="preprocessor">#define I2C1_GATING             BIT(1)</span></div><div class="line"><a name="l00029"></a><span class="lineno"><a class="line" href="sys_8h.html#ae6c60aed43b5c1732ef0b98b9091b02a">   29</a></span>&#160;<span class="preprocessor">#define I2C2_GATING             BIT(2)</span></div><div class="line"><a name="l00030"></a><span class="lineno"><a class="line" href="sys_8h.html#acfc972f15066e87293868bab13156a6a">   30</a></span>&#160;<span class="preprocessor">#define BUS_CLK_GATING_REG4         (CCM_BASE + 0x070)</span></div><div class="line"><a name="l00031"></a><span class="lineno">   31</span>&#160;</div><div class="line"><a name="l00032"></a><span class="lineno">   32</span>&#160;<span class="comment">/* soft reset */</span></div><div class="line"><a name="l00033"></a><span class="lineno"><a class="line" href="sys_8h.html#ab48c1d12882d92efe36ed5dbe994c8e6">   33</a></span>&#160;<span class="preprocessor">#define BUS_SOFT_RST_REG0       (CCM_BASE + 0x2c0)</span></div><div class="line"><a name="l00034"></a><span class="lineno"><a class="line" href="sys_8h.html#a7ab10819023ed2721029456e518d4a5e">   34</a></span>&#160;<span class="preprocessor">#define BUS_SOFT_RST_REG1       (CCM_BASE + 0x2c4)</span></div><div class="line"><a name="l00035"></a><span class="lineno"><a class="line" href="sys_8h.html#a9d38e1a6531a73c5543a27b100ce984a">   35</a></span>&#160;<span class="preprocessor">#define MSGBOX_RST          BIT(21)</span></div><div class="line"><a name="l00036"></a><span class="lineno"><a class="line" href="sys_8h.html#a34a8e2f2380172f0d2ad7d0b49770d75">   36</a></span>&#160;<span class="preprocessor">#define BUS_SOFT_RST_REG2       (CCM_BASE + 0x2c8)</span></div><div class="line"><a name="l00037"></a><span class="lineno"><a class="line" href="sys_8h.html#ad3fd6931c760ec63cacd85f974850870">   37</a></span>&#160;<span class="preprocessor">#define BUS_SOFT_RST_REG3       (CCM_BASE + 0x2d0)</span></div><div class="line"><a name="l00038"></a><span class="lineno"><a class="line" href="sys_8h.html#a28b1a98f4c4c6976a195f57370355f8d">   38</a></span>&#160;<span class="preprocessor">#define THS_RST             BIT(8)</span></div><div class="line"><a name="l00039"></a><span class="lineno"><a class="line" href="sys_8h.html#a534f4f0d558df21767e23d3f2839052f">   39</a></span>&#160;<span class="preprocessor">#define BUS_SOFT_RST_REG4       (CCM_BASE + 0x2d8)</span></div><div class="line"><a name="l00040"></a><span class="lineno"><a class="line" href="sys_8h.html#a887618b73301247b82f0d0ae88edb898">   40</a></span>&#160;<span class="preprocessor">#define UART0_RST           BIT(16)</span></div><div class="line"><a name="l00041"></a><span class="lineno"><a class="line" href="sys_8h.html#a33357ddd398f00221068a11fa16333ff">   41</a></span>&#160;<span class="preprocessor">#define I2C0_RST            BIT(0)</span></div><div class="line"><a name="l00042"></a><span class="lineno"><a class="line" href="sys_8h.html#a2b2f4c1ed9d2537f6c6c6e5200b6c381">   42</a></span>&#160;<span class="preprocessor">#define I2C1_RST            BIT(1)</span></div><div class="line"><a name="l00043"></a><span class="lineno"><a class="line" href="sys_8h.html#a6e4a65275dbe478990b7253215f24e98">   43</a></span>&#160;<span class="preprocessor">#define I2C2_RST            BIT(2)</span></div><div class="line"><a name="l00044"></a><span class="lineno">   44</span>&#160;</div><div class="line"><a name="l00045"></a><span class="lineno">   45</span>&#160;<span class="comment">/* apb2 */</span></div><div class="line"><a name="l00046"></a><span class="lineno"><a class="line" href="sys_8h.html#a38494e6a8dd91a4642edd884aaf6a6ed">   46</a></span>&#160;<span class="preprocessor">#define APB2_CFG_REG            (CCM_BASE + 0x058)</span></div><div class="line"><a name="l00047"></a><span class="lineno"><a class="line" href="sys_8h.html#a6c821adc0f9f13e356e6a38228a54001">   47</a></span>&#160;<span class="preprocessor">#define APB2_CLK_SRC_LOSC       (0x0 &lt;&lt; 24)</span></div><div class="line"><a name="l00048"></a><span class="lineno"><a class="line" href="sys_8h.html#a4eaacbf29c7cc006054a95331cc50714">   48</a></span>&#160;<span class="preprocessor">#define APB2_CLK_SRC_OSC24M     (0x1 &lt;&lt; 24)</span></div><div class="line"><a name="l00049"></a><span class="lineno"><a class="line" href="sys_8h.html#aee09744e4531ee093418af96047f9bd7">   49</a></span>&#160;<span class="preprocessor">#define APB2_CLK_SRC_PLL6       (0x2 &lt;&lt; 24)</span></div><div class="line"><a name="l00050"></a><span class="lineno"><a class="line" href="sys_8h.html#ade1bd2860870ed97a1d638a66ccf76d2">   50</a></span>&#160;<span class="preprocessor">#define APB2_CLK_SRC_MASK       (0x3 &lt;&lt; 24)</span></div><div class="line"><a name="l00051"></a><span class="lineno"><a class="line" href="sys_8h.html#ac1dd15a00dcbab6475f5cef51d82ad21">   51</a></span>&#160;<span class="preprocessor">#define APB2_CLK_RATE_N_1       (0x0 &lt;&lt; 16)</span></div><div class="line"><a name="l00052"></a><span class="lineno"><a class="line" href="sys_8h.html#a9766839361163a5c703c45865d56983c">   52</a></span>&#160;<span class="preprocessor">#define APB2_CLK_RATE_N_2       (0x1 &lt;&lt; 16)</span></div><div class="line"><a name="l00053"></a><span class="lineno"><a class="line" href="sys_8h.html#ade2ce9c66165f3bea29164cd3a456dca">   53</a></span>&#160;<span class="preprocessor">#define APB2_CLK_RATE_N_4       (0x2 &lt;&lt; 16)</span></div><div class="line"><a name="l00054"></a><span class="lineno"><a class="line" href="sys_8h.html#a336b66ba9d491aefce62bb89d17cdd46">   54</a></span>&#160;<span class="preprocessor">#define APB2_CLK_RATE_N_8       (0x3 &lt;&lt; 16)</span></div><div class="line"><a name="l00055"></a><span class="lineno"><a class="line" href="sys_8h.html#af4a16d9a7a0430c15be1eb3cb1658533">   55</a></span>&#160;<span class="preprocessor">#define APB2_CLK_RATE_N_MASK        (3 &lt;&lt; 16)</span></div><div class="line"><a name="l00056"></a><span class="lineno"><a class="line" href="sys_8h.html#af88e115225051626db54c7d28061e2a5">   56</a></span>&#160;<span class="preprocessor">#define APB2_CLK_RATE_M(m)      (((m)-1) &lt;&lt; 0)</span></div><div class="line"><a name="l00057"></a><span class="lineno"><a class="line" href="sys_8h.html#ab1aa9181a356bad6ef7856cb35a0df37">   57</a></span>&#160;<span class="preprocessor">#define APB2_CLK_RATE_M_MASK            (0x1f &lt;&lt; 0)</span></div><div class="line"><a name="l00058"></a><span class="lineno">   58</span>&#160;</div><div class="line"><a name="l00059"></a><span class="lineno">   59</span>&#160;<span class="comment">/* pll6 */</span></div><div class="line"><a name="l00060"></a><span class="lineno"><a class="line" href="sys_8h.html#abb89e65e2c302dfbd928cc869d90c07b">   60</a></span>&#160;<span class="preprocessor">#define PLL6_CTRL_REG           (CCM_BASE + 0x0028)</span></div><div class="line"><a name="l00061"></a><span class="lineno"><a class="line" href="sys_8h.html#a73ea57e64a35940d153a699dd9a21609">   61</a></span>&#160;<span class="preprocessor">#define PLL6_CTRL_ENABLE        BIT(31)</span></div><div class="line"><a name="l00062"></a><span class="lineno"><a class="line" href="sys_8h.html#a73f8d7563bb997e09f5aadfd4ade0ba6">   62</a></span>&#160;<span class="preprocessor">#define PLL6_CTRL_LOCK          BIT(28)</span></div><div class="line"><a name="l00063"></a><span class="lineno"><a class="line" href="sys_8h.html#a349e36a016b71389ed6368fae154a6bc">   63</a></span>&#160;<span class="preprocessor">#define PLL6_CTRL_BYPASS        BIT(25)</span></div><div class="line"><a name="l00064"></a><span class="lineno"><a class="line" href="sys_8h.html#a0c5e5cf80be52c0b0d5b0f4fa17b3144">   64</a></span>&#160;<span class="preprocessor">#define PLL6_CTRL_CLK_OUTEN     BIT(24)</span></div><div class="line"><a name="l00065"></a><span class="lineno"><a class="line" href="sys_8h.html#aacc8063a00f55aee34d9487181ee1532">   65</a></span>&#160;<span class="preprocessor">#define PLL6_CTRL_24M_OUTEN     BIT(18)</span></div><div class="line"><a name="l00066"></a><span class="lineno">   66</span>&#160;</div><div class="line"><a name="l00067"></a><span class="lineno">   67</span>&#160;<span class="comment">/* ths */</span></div><div class="line"><a name="l00068"></a><span class="lineno"><a class="line" href="sys_8h.html#a1e80e3ac490920cf8761b6ff62592124">   68</a></span>&#160;<span class="preprocessor">#define THS_CLK_REG                     (CCM_BASE + 0x0074)</span></div><div class="line"><a name="l00069"></a><span class="lineno"><a class="line" href="sys_8h.html#a9aff9c4c93ca6cbd92c243cbb6d223e6">   69</a></span>&#160;<span class="preprocessor">#define THS_CLK_SCLK_GATING             BIT(31)</span></div><div class="line"><a name="l00070"></a><span class="lineno"><a class="line" href="sys_8h.html#acb327f3c3edb1b719e3f8bc89e5304a3">   70</a></span>&#160;<span class="preprocessor">#define THS_CLK_SRC_OSC24M              0</span></div><div class="line"><a name="l00071"></a><span class="lineno"><a class="line" href="sys_8h.html#a965d98c76ad9e02deaf082314247ccff">   71</a></span>&#160;<span class="preprocessor">#define THS_CLK_DIV_RATIO_6             0x3</span></div><div class="line"><a name="l00072"></a><span class="lineno"><a class="line" href="sys_8h.html#af75c73ac00d4afcaff2020c198949e72">   72</a></span>&#160;<span class="preprocessor">#define THS_CLK_DIV_RATIO_1             0x0</span></div><div class="line"><a name="l00073"></a><span class="lineno">   73</span>&#160;</div><div class="line"><a name="l00074"></a><span class="lineno">   74</span>&#160;<span class="comment">/* pll1 */</span></div><div class="line"><a name="l00075"></a><span class="lineno"><a class="line" href="sys_8h.html#ae133cec95e2bcc3006f56490fce9969b">   75</a></span>&#160;<span class="preprocessor">#define PLL_CPUX_CTRL_REG               (CCM_BASE)</span></div><div class="line"><a name="l00076"></a><span class="lineno"><a class="line" href="sys_8h.html#ac516a49c0afdb264c2301ecb8766ea86">   76</a></span>&#160;<span class="preprocessor">#define PLL_CPUX_ENABLE                 BIT(31)</span></div><div class="line"><a name="l00077"></a><span class="lineno"><a class="line" href="sys_8h.html#ad12a5037c7c6c843395d9a68fce93123">   77</a></span>&#160;<span class="preprocessor">#define PLL_CPUX_LOCK                   BIT(28)</span></div><div class="line"><a name="l00078"></a><span class="lineno"><a class="line" href="sys_8h.html#a003b50cdbc30d82854bd17094a04d9e9">   78</a></span>&#160;<span class="preprocessor">#define PLL_CPUX_P(v)                   ((v) &lt;&lt; 16)</span></div><div class="line"><a name="l00079"></a><span class="lineno"><a class="line" href="sys_8h.html#ab49b183ccec500a45e89cc6316d1998e">   79</a></span>&#160;<span class="preprocessor">#define PLL_CPUX_N(v)                   ((v) &lt;&lt; 8)</span></div><div class="line"><a name="l00080"></a><span class="lineno"><a class="line" href="sys_8h.html#a70cf4795d9c2ed56fde24aa499c2c320">   80</a></span>&#160;<span class="preprocessor">#define PLL_CPUX_K(v)                   ((v) &lt;&lt; 4)</span></div><div class="line"><a name="l00081"></a><span class="lineno"><a class="line" href="sys_8h.html#a85e47fb00be7eadfc6c9f556bc54f529">   81</a></span>&#160;<span class="preprocessor">#define PLL_CPUX_M(v)                   ((v) &lt;&lt; 0)</span></div><div class="line"><a name="l00082"></a><span class="lineno">   82</span>&#160;</div><div class="line"><a name="l00083"></a><span class="lineno"><a class="line" href="sys_8h.html#a804771b9e4ebc24911e128e10db4d18a">   83</a></span>&#160;<span class="preprocessor">#define CPUX_AXI_CFG_REG                (CCM_BASE + 0x0050)</span></div><div class="line"><a name="l00084"></a><span class="lineno">   84</span>&#160;</div><div class="line"><a name="l00085"></a><span class="lineno">   85</span>&#160;<span class="comment">/*</span></div><div class="line"><a name="l00086"></a><span class="lineno">   86</span>&#160;<span class="comment"> * AR100 clock configuration register:</span></div><div class="line"><a name="l00087"></a><span class="lineno">   87</span>&#160;<span class="comment"> * [31:18] Reserved</span></div><div class="line"><a name="l00088"></a><span class="lineno">   88</span>&#160;<span class="comment"> * [17:16] Clock source (00: LOSC, 01: HOSC, 10/11: PLL6/PDIV)</span></div><div class="line"><a name="l00089"></a><span class="lineno">   89</span>&#160;<span class="comment"> * [15:13] Reserved</span></div><div class="line"><a name="l00090"></a><span class="lineno">   90</span>&#160;<span class="comment"> * [12:8]  Post divide (00000: 1 - 11111: 32)</span></div><div class="line"><a name="l00091"></a><span class="lineno">   91</span>&#160;<span class="comment"> * [7:6]   Reserved</span></div><div class="line"><a name="l00092"></a><span class="lineno">   92</span>&#160;<span class="comment"> * [5:4]   Clock divide ratio (00: 1, 01: 2, 10: 4, 11: 8)</span></div><div class="line"><a name="l00093"></a><span class="lineno">   93</span>&#160;<span class="comment"> * [3:0]   Reserved</span></div><div class="line"><a name="l00094"></a><span class="lineno">   94</span>&#160;<span class="comment"> */</span></div><div class="line"><a name="l00095"></a><span class="lineno"><a class="line" href="sys_8h.html#a7276a9401b934ed585122f7dccb6d007">   95</a></span>&#160;<span class="preprocessor">#define AR100_CLKCFG_REG        (R_PRCM_BASE + 0x000)</span></div><div class="line"><a name="l00096"></a><span class="lineno"><a class="line" href="sys_8h.html#afbcf720ba08a8b753a0ed4c7f72b26e2">   96</a></span>&#160;<span class="preprocessor">#define AR100_CLKCFG_SRC_LOSC       (0 &lt;&lt; 16)</span></div><div class="line"><a name="l00097"></a><span class="lineno"><a class="line" href="sys_8h.html#acd3be5c43881264dce0df237304a47e1">   97</a></span>&#160;<span class="preprocessor">#define AR100_CLKCFG_SRC_HOSC       (1 &lt;&lt; 16)</span></div><div class="line"><a name="l00098"></a><span class="lineno"><a class="line" href="sys_8h.html#af1c48279ab37fed0d6c91b16b0060232">   98</a></span>&#160;<span class="preprocessor">#define AR100_CLKCFG_SRC_PLL6       (2 &lt;&lt; 16)</span></div><div class="line"><a name="l00099"></a><span class="lineno"><a class="line" href="sys_8h.html#a698918fbd564563df2268fa10e9f070d">   99</a></span>&#160;<span class="preprocessor">#define AR100_CLKCFG_SRC_MASK       (0x3 &lt;&lt; 16)</span></div><div class="line"><a name="l00100"></a><span class="lineno"><a class="line" href="sys_8h.html#a42b44047c5b79fc12f0694172cf58ca0">  100</a></span>&#160;<span class="preprocessor">#define AR100_CLKCFG_POSTDIV(x)     (((x) &amp; 0x1f) &lt;&lt; 8)</span></div><div class="line"><a name="l00101"></a><span class="lineno"><a class="line" href="sys_8h.html#a57aa3943b1cb1f15a0936256ef3a9f6c">  101</a></span>&#160;<span class="preprocessor">#define AR100_CLKCFG_POSTDIV_MASK   (0x1f &lt;&lt; 8)</span></div><div class="line"><a name="l00102"></a><span class="lineno"><a class="line" href="sys_8h.html#a60d05018344fbf75939b649f65dbe3aa">  102</a></span>&#160;<span class="preprocessor">#define AR100_CLKCFG_DIV(x)     (((x) &amp; 0x3) &lt;&lt; 4)</span></div><div class="line"><a name="l00103"></a><span class="lineno"><a class="line" href="sys_8h.html#a8da446c07b6a2ab2687123d4a8f47658">  103</a></span>&#160;<span class="preprocessor">#define AR100_CLKCFG_DIV_MASK       (0x3 &lt;&lt; 4)</span></div><div class="line"><a name="l00104"></a><span class="lineno">  104</span>&#160;</div><div class="line"><a name="l00105"></a><span class="lineno"><a class="line" href="sys_8h.html#a54b40c39c89be3adecbf89bd8de62509">  105</a></span>&#160;<span class="preprocessor">#define R_PRCM_CLK_GATING_REG       (R_PRCM_BASE + 0x28) // ???</span></div><div class="line"><a name="l00106"></a><span class="lineno"><a class="line" href="sys_8h.html#a31471c7c734df5e92c7530fc5479d9f0">  106</a></span>&#160;<span class="preprocessor">#define R_PIO_GATING            BIT(0)</span></div><div class="line"><a name="l00107"></a><span class="lineno">  107</span>&#160;</div><div class="line"><a name="l00108"></a><span class="lineno">  108</span>&#160;<span class="comment">// ARISC/CPUS and RTC power regulation</span></div><div class="line"><a name="l00109"></a><span class="lineno"><a class="line" href="sys_8h.html#a862629a59ac3d2e7d95806773affdede">  109</a></span>&#160;<span class="preprocessor">#define VDD_RTC_REG 0x01f00190</span></div><div class="line"><a name="l00110"></a><span class="lineno">  110</span>&#160;</div><div class="line"><a name="l00111"></a><span class="lineno">  111</span>&#160;</div><div class="line"><a name="l00112"></a><span class="lineno">  112</span>&#160;</div><div class="line"><a name="l00113"></a><span class="lineno">  113</span>&#160;</div><div class="line"><a name="l00114"></a><span class="lineno">  114</span>&#160;<span class="keywordtype">void</span> <a class="code" href="sys_8h.html#aa0dc7fa903cefe8f15538560fa39b3e6">enable_caches</a>(<span class="keywordtype">void</span>);</div><div class="line"><a name="l00115"></a><span class="lineno">  115</span>&#160;<span class="keywordtype">void</span> <a class="code" href="sys_8h.html#a3aea9deb2a0bfea9ff05a898f4822e31">reset</a>(<span class="keywordtype">void</span>);</div><div class="line"><a name="l00116"></a><span class="lineno">  116</span>&#160;<span class="keywordtype">void</span> <a class="code" href="sys_8h.html#af59d0d8f73d45a75846edc13e148e834">handle_exception</a>(uint32_t type, uint32_t pc, uint32_t sp);</div><div class="line"><a name="l00117"></a><span class="lineno">  117</span>&#160;<span class="keywordtype">void</span> <a class="code" href="sys_8h.html#a4742c7e9dfbaaa110557fc0e3067a622">clk_set_rate</a>(uint32_t rate);</div><div class="line"><a name="l00118"></a><span class="lineno">  118</span>&#160;</div><div class="line"><a name="l00119"></a><span class="lineno">  119</span>&#160;</div><div class="line"><a name="l00120"></a><span class="lineno">  120</span>&#160;</div><div class="line"><a name="l00121"></a><span class="lineno">  121</span>&#160;</div><div class="line"><a name="l00122"></a><span class="lineno">  122</span>&#160;<span class="preprocessor">#endif</span></div><div class="ttc" id="sys_8h_html_a3aea9deb2a0bfea9ff05a898f4822e31"><div class="ttname"><a href="sys_8h.html#a3aea9deb2a0bfea9ff05a898f4822e31">reset</a></div><div class="ttdeci">void reset(void)</div><div class="ttdef"><b>Definition:</b> sys.c:22</div></div>
<div class="ttc" id="sys_8h_html_a4742c7e9dfbaaa110557fc0e3067a622"><div class="ttname"><a href="sys_8h.html#a4742c7e9dfbaaa110557fc0e3067a622">clk_set_rate</a></div><div class="ttdeci">void clk_set_rate(uint32_t rate)</div><div class="ttdef"><b>Definition:</b> sys.c:36</div></div>
<div class="ttc" id="sys_8h_html_af59d0d8f73d45a75846edc13e148e834"><div class="ttname"><a href="sys_8h.html#af59d0d8f73d45a75846edc13e148e834">handle_exception</a></div><div class="ttdeci">void handle_exception(uint32_t type, uint32_t pc, uint32_t sp)</div><div class="ttdef"><b>Definition:</b> sys.c:28</div></div>
<div class="ttc" id="sys_8h_html_aa0dc7fa903cefe8f15538560fa39b3e6"><div class="ttname"><a href="sys_8h.html#aa0dc7fa903cefe8f15538560fa39b3e6">enable_caches</a></div><div class="ttdeci">void enable_caches(void)</div><div class="ttdef"><b>Definition:</b> sys.c:9</div></div>
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